Ethernet local area network (LAN) systems are becoming increasingly popular because the open standards associated with ethernet systems make this network available to almost everyone having a desire for networked computer systems. An ethernet interface can normally operate at 10 megabits per second (Mbps), and at fast ethernet speeds the interface operates at 100 Mbps, making it suitable for a wide variety of applications. Different computers can be linked with vendor-neutral network technology. The ethernet standard is formalized as IEEE 802.3 Carrier Sense Multiple Access with Collision Detection (CSMA/CD) access method of the physical layer specifications developed by the Institute of Electrical and Electronic Engineers, and adopted by the International Organization for Standardization (ISO). The ethernet system includes a physical medium to carry the ethernet packet signals between computers, a set of medium access control rules embedded in each ethernet interface, and an ethernet frame or packet that is a standardized set of bits to carry data over the system.
An ethernet system includes a number of Data Terminal Equipment (DTE), typically computers, which are connected in the network. Each Data Terminal Equipment includes a port having a physical layer and a Media Access Control (MAC) typically connected by an n-pin connector (e.g., a 40-pin connector), via a media independent interface (MII), to a physical layer device (PHY), such as a transceiver, as known to those skilled in the art. This ethernet device includes a First-In, First-Out (FIFO) buffer that is also operable with a Medium Dependent Interface (MDI), such as a twisted-pair connector or fiberoptic connector. A typical connector includes an RJ-45 connector connected to the physical medium that carries the ethernet signals. Other optical connectors can also be used, depending on the design.
As known to those skilled in the art, an inter-packet gap (IPG) space is required as the FIFO buffer receives and empties data from packets. A physically-large FIFO buffer cannot be used in ethernet applications because a larger FIFO buffer violates the smallest possible inter-packet gap (IPG) space as the buffer receives the packets. The FIFO buffers are necessary when used with a media independent interface (MII), including a serial mode independent interface (SMII) and reduced media independent interface (RMII). The standard system clock is driven from the media access control (MAC), which implements two clock domains. Thus, data is buffered through the FIFO buffer. Because the time separation between clock domains is small, the FIFO buffers used in the ethernet systems are not large and can be about 64 bits.
In prior art devices, the FIFO buffer was always receiving data until it was half-full and configured to work with a half-full pointer. Thus, a good portion of the FIFO buffer remained unused and the inter-packet gap (IGP) space size was not efficiently configured.